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product highlights ecosmart ? - energy effcient ? multi-mode control maximizes effciency over full load range ? no-load consumption below 30 mw at 230 vac (lnk67xx) ? >75% effciency with 1 w input at 230 vac ? >50% effciency with 0.1 w input at 230 vac high design flexibility for low system cost ? dramatically simplifes power supply designs ? eliminates optocoupler and all secondary control circuitry ? 5% or better output voltage tolerance ? 132 khz operation reduces transformer and power supply size ? accurate programmable current limit ? compensation over line limits overload power ? frequency jittering reduces emi flter cost ? fully integrated soft-start for minimum start-up stress ? 725 v mosfet simplifes meeting derating requirements (lnk677x) ? 650 v mosfet for lowest system cost (lnk676x/lnk666x) ? fast transient response family option (lnk666x) extensive protection features ? auto-restart limits power delivery to 3% during overload faults ? output short-circuit protection (scp) ? output overload/over-current protection (opp, ocp) ? optional extended shutdown delay time ? output overvoltage protection (ovp), auto-restart or latching ? line brown-in/out protection (line uv) ? line overvoltage (ov) shutdown extends line surge withstand ? accurate thermal shutdown (otp), hysteretic or latching advanced green package options ? esip ? -7c package: ? vertical orientation for minimum pcb footprint ? simple heat sink mounting using clip or adhesive pad ? esop ? -12b package: ? low profle surface mounted for ultra-slim designs ? heat transfer to pcb via exposed pad and source pins ? supports either wave or ir refow soldering ? edip ? -12b package: ? low profle through-hole mounted for ultra-slim designs ? heat transfer to pcb via exposed pad or optional metal heat sink ? extended creepage to drain pin ? heat sink is connected to source for low emi ? halogen free and rohs compliant typical applications ? lcd monitor and tv ? adapter ? appliances ? embedded power supplies (dvd, set-top box) ? industrial figure 1. typical application schematic. control figure 2. package options. exposed pad esop-12b (k package) edip-12b (v package) esip-7c (e package) output power table product 4 heat sink 230 vac 15% 85-265 vac adapter open frame adapter open frame lnk6xx3k/v pcb-w 1 15 w 25 w 9 w 15 w lnk6xx3k pcb-r 2 21 w 35 w 12 w 21 w lnk6xx3e metal 21 w 35 w 13 w 27 w lnk6xx4k/v pcb-w 1 16 w 28 w 11 w 20 w lnk6xx4k pcb-r 2 22 w 39 w 15 w 28 w lnk6xx4e metal 30 w 47 w 20 w 36 w lnk6xx5k/v pcb-w 1 19 w 30 w 13 w 22 w lnk6xx5k pcb-r 2 26 w 42 w 18 w 31 w lnk6xx5e metal 40 w 59 3 w 26 w 45 w lnk6xx6k/v pcb-w 1 21 w 34 w 15 w 26 w lnk6xx6k pcb-r 2 30 w 48 w 22 w 37 w lnk6xx6e metal 60 w 88 3 w 40 w 68 3 w lnk6xx7k/v pcb-w 1 25 w 41 w 19 w 30 w lnk6xx7k pcb-r 2 36 w 59 w 27 w 43 w lnk6xx7e metal 85 3 w 117 3 w 55 w 90 3 w table 1. output power table. notes: 1. pcb heat sink with wave soldering. 2. pcb heat sink with ir refow soldering (exposed pad thermally connected to pcb). 3. maximum power specifed based on proper thermal dissipation. 4. packages: e: esip-7c, k: esop-12b, v: edip-12b. see table 2 for all device options. exposed pad www.powerint.com march 2014 linkswitch-hp family energy effcient, high-power off-line switcher with accurate primary-side regulation (psr) ? this product is covered by patents and/or pending patent applications.
2 figure 3. block diagram. table 2. device part numbers and options. notes: 1. minimum breakdown voltage at t j = +25 c. 2. t mcm(off) = 0.5 ms for fastest transient response, t mcm(off) = 4 ms for <30 mw no-load input power. pi-6565-072012 clock oscillator line compensation line overvoltage/ undervoltage detection 5.75 v 4.9 v 40% ~ 100% high gain trans- conductance amplifier error voltage multi-cycle mode control output overvoltage auto-restart latch/hysteretic 2 v reference voltage gate driver current limit comparator source (s) s r q dc max osc bypass (bp) leb + - drain (d) compensation (cp) q feedback (fb) + 5.75 v regulator fault filter program/ delay (pd) + program i lim current limit setting thermal shutdown bypass program luv lov s/h ov auto- restart + line comp amp mcm soft- start custom shutdown delay lnk 6 x x x e/v/k part number series t mcm(off) 2 6 = 0.5 ms 7 = 4.0 ms bv dss 1 6 = 650 v 7 = 725 v power packages lnk6663e/v/k 6 0.5 ms 650 v device size esip-7c (e), edip-12b (v), esop-12b (k) lnk6664e/v/k 0.5 ms 650 v esip-7c (e), edip-12b (v), esop-12b (k) lnk6665e/v/k 0.5 ms 650 v esip-7c (e), edip-12b (v), esop-12b (k) lnk6666e/v/k 0.5 ms 650 v esip-7c (e), edip-12b (v), esop-12b (k) lnk6667e/v/k 0.5 ms 650 v esip-7c (e), edip-12b (v), esop-12b (k) lnk6763e/v/k 4.0 ms 650 v esip-7c (e), edip-12b (v), esop-12b (k) lnk6764e/v/k 4.0 ms 650 v esip-7c (e), edip-12b (v), esop-12b (k) lnk6765e/v/k 4.0 ms 650 v esip-7c (e), edip-12b (v), esop-12b (k) lnk6766e/v/k 4.0 ms 650 v esip-7c (e), edip-12b (v), esop-12b (k) lnk6767e/v/k 4.0 ms 650 v esip-7c (e), edip-12b (v), esop-12b (k) lnk6773e/v/k 4.0 ms 725 v esip-7c (e), edip-12b (v), esop-12b (k) lnk6774e/v/k 4.0 ms 725 v esip-7c (e), edip-12b (v), esop-12b (k) lnk6775e/v/k 4.0 ms 725 v esip-7c (e), edip-12b (v), esop-12b (k) lnk6776e/v/k 4.0 ms 725 v esip-7c (e), edip-12b (v), esop-12b (k) lnk6777e/v/k 4.0 ms 725 v esip-7c (e), edip-12b (v), esop-12b (k) rev. c 03/14 linkswitch-hp www.powerint.com www.powerint.com
3 figure 4. pin confguration. pin functional description bypass (bp) pin: an external bypass capacitor is connected to this pin for the internally generated 5.75 v supply. based on the connected capacitance determined at start-up, it will provide either auto-restart or latching shutdown option dependant on the fault condition. please see table 3. compensation (cp) pin: this pin is the output of transconductance amplifer. an rc compensation network on this pin provides control loop compensation. drain (d) pin: this pin is the high-voltage power mosfet drain connection. it also provides internal operating current for start-up until output is in regulation. feedback (fb) pin: the feedback pin is used to sense output and input voltage by sensing the auxiliary winding voltage. during mosfet on-time, the current out of the feedback pin is sensed to detect the line voltage. during the secondary rectifer conduction time, the feedback voltage is proportional to the output voltage via the turns ratio between the bias and secondary windings. program (pd) pin: this multi-functional pin sets device current limit and optional shutdown delay time extension. during start-up, the internal circuit decodes the current limit based on resistor loaded on the program pin. please see table 4. it can also be used for optionally extending shutdown delay time by changing the capacitance on the pin. see figure 6. source (s) pin: this pin is the power mosfet source connection. it is also the ground reference for the bypass, feedback, program and compensation pins. functional description a linkswitch-hp device monolithically integrates a controller and high-voltage power mosfet into one package. it has a newly developed analogue control scheme, which enables continuous conduction mode (ccm), primary side regulated (psr) power supplies up to 90 w without the effciency limitation of dcm or audible noise. it uses an enhanced peak current mode pwm control scheme with multi-mode operation. the multi-mode control engine uses the error amplifer output signal voltage at the compensation pin to set the operating peak current and switching frequency to maintain the output voltage in regulation as shown in figure 5. for compensation pin voltages lower than v c(mcm) (typ. 1.25 v) the device enters multi-cycle modulation (mcm) with a fxed peak current of 25% of the programmed current limit. several innovative improvements have been added to the peak current mode control to allow primary side regulated ccm operation with no instability. the device meets less than 30 mw input power with no-load at high-line (lnk67xx families). it also offers extensive built-in features: ? external current limit selection. ? optional programmable shutdown delay time extension. ? optional remote on/off. ? optional fast ac reset. ? primary-side sensed output overvoltage protection (ovp) . ? lost regulation protection during output overload or short-circuit (auto-restart). ? internal current limit over line compensation for constant overload power over line. ? high-voltage bus overvoltage sense (line ov) for extended line surge withstand. ? high-voltage bus undervoltage sense (line uv) for brown-in/ out protection. ? accurate over-temperature protection (otp). ? output ovp/ocp/otp shutdown type selection (hysteretic/ latching). ? optional external latching shutdown input (current threshold) ? cycle-by-cycle current limit control. regulator/shunt voltage clamp the internal 5.75 v regulator charges the bypass capacitor connected to the bypass pin to 5.75 v by drawing a current from drain whenever the power mosfet is off. when the power mosfet is on, the device operates from the energy stored in the bypass capacitor. in addition, there is a shunt regulator clamping the bypass at 6.4 v when supply current is provided by a bias winding through an external resistor. this makes the device insensitive to bias winding voltage variations. 12 s 11 s 10 s 9 s 8 s 7 s pd 1 fb 2 cp 3 bp 4 d 6 pi-6564-081412 e package (esip-7c) k package (esop-12b) exposed pad (on bottom) internally connected to source pin exposed pad (hidden) internally connected to source pin 7 d 5 s 4 b p 3 c p 2 f b 1 p d 1 pd 2 fb 3 cp 4 bp 6 d s 12 s 11 s 10 s 9 s 8 s 7 v package (edip-12b) exposed pad internally connected to source pin rev. c 03/14 www.powerint.com linkswitch-hp
4 auto-restart in the event of an open-loop fault (no connection between the feedback winding and the feedback divider network or the feedback pin to the feedback network), the sensed current out of feedback pin will be zero during mosfet on-time, the device enters into line brown-out protection (line uv). in the event of output short-circuit or overload condition, the device enters into auto-restart mode. auto-restart minimizes the power dissipation under fault conditions, the device will turn on and off at duty cycle of typically 3% as long as the fault condition persists. in auto-restart switching is disabled for t ar(off)1 (typ. 150 ms) when the feedback pin voltage has dropped below the auto-restart threshold v fb(ar) for the shutdown default delay time t ar(on) (typ. 35 ms). after this period switching is enabled again with the device entering soft-start (typ. 15 ms). for the frst auto-restart off-period switching is disabled for a reduced time t ar(off)2 (typ. 1500 ms) to reduce the power supply restart time during line cycling. optionally the default shutdown delay time can be extended by adding a capacitor to the program pin. hysteretic thermal shutdown the thermal shutdown circuitry senses the controller die temperature. the threshold is set at 142 c with a 75 c hysteresis (both typical). once the device temperature rises above 142 c, the power mosfet is disabled and remains disabled until the die temperature falls by 75 c, at which point the device is re-enabled. the large hysteresis maintain the average temperature below the temperature rating of low cost cem type pcb material in most cases. safe operating area (soa) protection the device features a safe operating area (soa) protection mode which disables mosfet switching for 4 consecutive cycles in the event the peak switching current reaches the current limit in less than time t on(soa) . this prevents excessive drain currents during start-up and output short-circuit conditions by providing additional time for the primary inductance to reset. the soa protection is disabled when the output voltage is within 7.5% of regulation voltage. sample and hold (s/h) the sample and hold block senses the output voltage at auxiliary winding during secondary rectifer on-time. the feedback pin voltage is sampled after the turn-off of the internal switch to compensate for diode conduction time differences. sampling time increases monotonically from 1.2 m s at no or light load to 2.5 m s at full load. sampled voltage is held until the next clock cycle. the output of s/h is fed to the error amplifer, once in regulation the sampled voltage is 2 v. bypass (bp) programming this feature selects either hysteretic or latching ovp/ocp and otp protection based on capacitor loading on the bypass pin. the shutdown type is determined at the device power-up as shown in table 3. current limit setting during power-up the cycle-by-cycle current limit is determined by measuring the resistor value connected to the program pin by the measurement is performed by applying 1.25 v (see figure 10). the current limit can be set between 40% to 100% in steps of 10% as shown in table 4. after the current limit is set the program pin voltage is reduced to ~0 in order to minimize power dissipation. programmable shutdown delay the default auto-restart shutdown delay time t sd(ar) (typ. 35 ms) can optionally be extended by connecting a capacitor to the program pin. once a lost regulation fault is detected the program pin voltage is cycled 128 times between v pd(dl) (typ. 0.5 v) and v pd(du) (typ. 1.2 v) as shown in figure 10. figure 6 depicts the relationship between extended shutdown delay time, added program pin capacitor and current limit programming resistor. figure 5. compensation pin characteristics (multi-mode operation). f sw(lf) v c(max) v c(min) v c(mcm) 32 132 100% 50% 25% pi-6722-111212 frequency (khz) compensation voltage ( p out ) compensation voltage ( p out ) normalized peak current i pd r pd i limit (norm) i pd r pd i limit (norm) m a k w % m a k w % 10 124 100 54 23.2 60 16 78.7 90 83 15.0 50 24 52.3 80 125 10.0 40 36 34.8 70 table 4. current limit selection vs. program pin resistor value. c bp 0.47 m f 4.7 m f 47 m f ovp latching auto-restart latching lost regulation (sc, oc) auto-restart auto-restart latching otp latching hysteretic latching table 3. shutdown type vs. value of bypass pin capacitance. rev. c 03/14 linkswitch-hp www.powerint.com www.powerint.com
5 remote on/off and fast ac reset the program pin can be used to turn on/off the device remotely. if the voltage on the pin is set to 1.35 v externally, the device stops switching. after releasing the program pin the program pin device commences switching when the voltage drops below 0.535 v. the program pin can also be used to reset the device latch after a latching ovp or otp event. if the voltage on the pin is set to 3.4 v externally, the device latch is reset. once the voltage drops below 0.535 v, device will start switching. high-voltage bus sensing linkswitch-hp senses indirectly the hv voltage bus v bus during the power mosfet on-time by monitoring the current fowing out of the feedback pin. during the mosfet on-time the voltage across the auxiliary winding is proportional to the voltage across the input winding. the current fowing through resistor r fb1 (see figure 8) is therefore representing v bus . indirect line sensing minimizes power dissipation and is used for line uv or line ov protection and current limit compensation over line. at power-up the current out of the feedback pin has to exceed the line undervoltage turn-on threshold (brown-in) current i fb(uvref) = -250 m a (typ.) before switching is enabled. during normal operation switching is disabled if the feedback pin current falls below the line undervoltage turn-off threshold (brown-out) current i fb(uvoff) = -100 m a (typ.) for at least 8 consecutive switching cycles. after switching has ended, the device enters auto-restart. the applicable auto-restart off- period t ar(off) 1 = 150 ms (typ.). switching is also stopped if the feedback pin current exceeds the line overvoltage threshold current i fb(ov) = -1.15 ma (typ.) for at least 2 consecutive switching cycles. current limit compensation over line the high-voltage bus is sensed by means of measuring the current out of the feedback pin during the mosfet on-time. to limit available overload power over line the set current limit is compensated as shown in figure 7. the compensation is disabled at peak currents below 50% of the set current limit, and is re-enabled at 62.5% of the set current limit. soft-start a digital soft-start is implemented to reduce component stress at power supply start-up. the internal reference voltage will ramp up to 2 v during t soft (typ. 15 ms) at start-up. the loop will typically close (output reaches regulation) during this time to ensure smooth output voltage rise. fault filter this is the digital flter to handle all the fault conditions including line overvoltage, line undervoltage, output overvoltage, and output undervoltage, thermal shutdown as well as package level fault (pin open-circuit or pin to pin short-circuit). transconductance amplifer the controller uses a high gain (typ. 70 db) transconductance amplifer to ensure exceptional output regulation. figure 7. current limit compensation over line. figure 8. indirect high-voltage bus sensing. figure 6. optional shutdown time extension programming. 0 50 100 150 200 250 300 350 400 450 500 pi-6646-040412 11 0 100 program pin capacitor v alue (nf) auto-restart on-t ime extension (ms) 124 k program pin resistor v alue 78.7 k 52.3 k 34.8 k 23.2 k 10.0 k 15.0 k v o v aux r fb1 u1 v fb v bus v sec r fb2 n a t1 n s d c o n p pi-6837-120312 d s fb bp cp pd control -150 -300 -450 -600 -750 -1050 -1200 -900 feedback pin current during mosfet on-time normalized set current limit (%) 110 100 90 80 70 pi-6721-040412 rev. c 03/14 www.powerint.com linkswitch-hp
6 figure 9. line sensing and auto-restart flow chart. pi-6838-101812 rev. c 03/14 linkswitch-hp www.powerint.com www.powerint.com ye s ye s ye s ye s ye s ye s no no no no 1. startup no no no no no no no no no no ye s 2. latching shutdown? (c bf = 47 f) 11. ac present? (i fb > -250 a) 14. line ov? (i fb > -1.15 ma for 2 cycles) 15. brown-out? (i fb < -100 a for 8 cycles) 16. regulation lost? (v fb < 1.85 v for 35 ms) 9. latch reset? (v pd > 3.4 v) 8. stop switching 10. reset latch 21. line ov? (i fb > 1.15 ma for 2 cycles) 22. brown-out? (i fb < -100 a for 8 cycles) ye s 17. stop switching 18. pause 150 ms (auto-restart off period t ar(off)1 ) 23. regulation lost? (v fb < 1.85 v for 35 ms) 24. stop switching 19. ac present? (i fb > -250 a) 25. pause 1500 ms (auto-restart off period t ar(off)2 ) 3. ac present? (i fb > -250 a) 5. line ov? (i fb > -1.15 ma for 2 cycles) 6. brown-out? (i fb < -100 a for 8 cycles) 7. regulation lost? (v fb < 1.85 v for 35 ms) ye s 26. pause 150 ms (auto-restart off period (t ar(off) ) 4. start switching (with 15 ms soft-start) 27. pause 150 ms (auto-restart off period t ar(off)1 ) 12. start switching (with 15 ms soft-start) 20. start switching (with 15 ms soft-start) ye s ye s ye s ye s
7 figure 10. program (pd) pin timing diagram. v pdthacr 3.40 v t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t pdst id i limit t pd programmable shutdown delay v fb sw v pdthrm 1.35 v v pdi v pdthpdh 1.25 v v pdthpdl 0.535 v pi-6692-101713 fast ac reset remote on/off osc this is an adjustable frequency oscillator. based on error voltage, the frequency will adjust from 32 khz at light load to 132 khz at heavy load. the oscillator employes 5 khz frequency jitter to reduce emi levels. current limit comparator this is a high-speed current limit comparator. it compares the current from the power mosfet to the internal current reference. once the current reaches the threshold the mosfet on-cycle is terminated. multi-cycle modulation (mcm) when voltage on compensation pin reaches v c(mcm) (about 1.25 v) the peak drain current is reduced to 25% of programmed value and the switching frequency approaches f mcm = 32 khz (typical). during mcm operation the controller intelligently maintains a relatively high output sampling rate while reducing the average switching frequency to keep the output voltage in regulation. switching at 25% of the set current limit reduces the transformer core fux density signifcantly. this and the intelligent mcm operation reduce audible noise well below acceptable levels. lnk666x has a maximum mcm off-time t mcm(off) = 0.5 ms (typ.). the high minimum output sampling rate provides excellent transient load response from 0% to 50% or 100% of nominal load while offering typically below 100 mw no-load input power. lnk67xx has a maximum mcm off-time t mcm(off) = 4 ms (typ.). the lower minimum output sampling rate enables designs below 30 mw no-load input power while providing fair transient load performance for load steps from 0% to 50% or 100% of nominal load. rev. c 03/14 www.powerint.com linkswitch-hp
8 applications example 30 w, 12 v universal adapter the circuit shown in figure 11 is a high effciency universal input 30 w, 12 v output adapter using the lnk6766e. the supply uses primary winding coupled sensing for the following features: output regulation, line undervoltage lockout, input and output ovp. with primary winding sense there is no need for an external secondary referenced error amplifer such as a tl431 and optocoupler. the winding sense of bus voltage also eliminates the need for direct input voltage sensing which requires more components and is more dissipative than winding sense method. output regulation is 5%, active-on effciency is 86% and no-load input power is less than 30 mw. the rectifed and fltered input voltage is applied to the primary winding of t1. the other side of the primary is driven by the integrated power mosfet in u1. diode d1, c3, r2, r3 and vr1 comprise the clamp circuit, limiting the leakage inductance turn-off voltage spike to safe value. zener diode vr1 also helps to reduce input power consumption during no-load conditions. start-up of the power supply is initiated by sensing the forward negative pulse current from feedback winding through r19 into figure 11. schematic of a universal input 30 w, 12 v, 2.5 a adapter. the feedback pin. this sensing is accomplished by periodically turning on the power mosfet to sense input voltage condition with very short low frequency sampling pulses. during the forward pulse sampling time the feedback pin is held to zero volts by an internal clamp. when negative forward pulse current exceeds 250 m a, linkswitch-hp for two consecutive switching cycles will initiate start-up with a soft-start sequence that reduces component stress and allows the output to rise in a smooth monotonic manner. the desired input voltage for start-up is determined by the turns ratio of primary winding to feedback winding and the value of r19. regulation is accomplished by sampling the feedback winding during fyback period through the resistor divider r19 and r20 through feedback pin. this sampled voltage is compared to an internal error amplifer threshold of 2 v. the value of r19 is already determined by the line undervoltage function so the output regulation point is determined by setting the proper value for r20. the loop compensation is provided by the network from compensation pin to ground. in the case above, a low frequency to mid frequency gain of 20 db for the error amplifer is established by r7 and c7. capacitor c8 functions essentially as a noise flter and is typically 100 pf. there is also an internal 16 khz flter within the device. it is advised to limit r7 to no greater than 260 k w to avoid stability and noise sensitivity. pi-6844-120312 c18 2.2 nf 250 vac vr1 bzg03c130 130 v l4 10 mh br2 df206st-g 600 v c2 68 f 400 v d2 bav21ws- 7-f t1 rm8 d1 dl4937 c6 22 f 16 v c8 100 pf 50 v c23 10 pf 50 v c20 4.7 nf 50 v c3 10 nf 630 v c12 1000 f 16 v c13 680 pf 100 v d8 stps30100st c5 470 nf 50 v 7 fl2 fl1 9 6 8 c14 150 nf 275 vac r29 3.3 m? r30 3.3 m? f1 2 a 90 - 265 vac 12 v, 2.5 a j3 rtn j4 j1 j2 linkswitch-hp d s fb bp cp pd control u1 lnk6766e c22 10 f 16 v l5 100 h r19 41.2 k? 1% r8 23.2 k? 1% 1/8 w r7 100 k? 1/8 w r9 4.3 k? 1% 1/8 w r13 20 ? 1/8 w r2 100 ? 1/2 w r3 3 k? r28 27 k? r20 10.2 k? 1% c7 100 nf 25 v rev. c 03/14 linkswitch-hp www.powerint.com www.powerint.com
9 the transient load response is dependent on the loop gain and minimum switching frequency. the values of r7 and c7 shown here typically give good transient response for most designs. when the supply is at no-load, the minimum switching frequency at no-load will create a delay to respond to any step load event during the off-time. in the case above, the minimum frequency is 250 hz so there is a potential 4 ms delay to response. if a faster response is desired from no-load initial condition there is the option to use the lnk666x which has a minimum frequency of 2 khz. there is a trade-off in using this family as no-load input power will be slightly higher and a smaller pre-load resistor will be required. in order to have good effciency, regulation performance and stability, the transformer leakage inductance should be minimized. low leakage will minimize ringing on the sense winding which can create an error in the feedback sampling. the example above uses split primary winding technique to lower leakage inductance. leakage inductance should not be greater than 2% of nominal primary inductance and 1% is typically the desirable target value. resistor r28 serves as a pre-load resistor to minimize output voltage rising in no-load condition. the pre-load resistor should be no smaller than is necessary to maintain output within specifcation limits to minimize added dissipation. in this example, the added pre-load dissipation is only 4.8 mw. linkswitch-hp provides an internal current source to bias the bypass pin which is necessary for start-up. when the supply is operating and in regulation an external bias is provided from the rectifed fyback voltage from the bias winding (d2 and c6). resistor r9 is sourced from the bias voltage across c6 into the bypass pin to provide external bias. the external bias current should set via r9 to be at least 500 m a to guarantee the internal current source of linkswitch-hp is turned off as this will allow the supply to operate more effciently, especially at light load. for best no-load performance the external supply voltage across c6 should be minimized (typically 8-9 v) and the current into the bypass pin set by r9 should be as low as possible. input overvoltage protection is done through sensing the negative forward pulse of feedback winding. when the negative forward voltage is suffciently high to produce more than 1.15 ma current into the feedback pin, for 2 consecutive on-cycles the device will stop switching for auto-restart delay period. output overvoltage protection is achieved by sensing the fyback pulse through the feedback pin. when the feedback pin sees 2.5 v or greater for 16 consecutive cycles, the supply will latch off. if non-latching ovp is desired then changing c5 from 0.47 m f to 4.7 m f will change fault mode accordingly (see table 3 for details). ocp protection is accomplished by sensing when the output drops below 0.925 of nominal regulation value for a duration greater than specifed delay time. in the example above, the total delay time is about 50 ms. capacitor c20 extends the default internal delay time of 35 ms (see figure 6 for details). the latching shut-off option is used in the design above. the primary current limit of linkswitch-hp can be adjusted by selecting the value for r8 (see table 4 for details). for this design 60% of maximum current limit was chosen. a lower current limit setting is typical for an adapter where lower r ds(on) is desirable for higher effciency and also lower thermal rise of linkswitch-hp. rev. c 03/14 www.powerint.com linkswitch-hp
10 layout considerations for esip-7c package figure 12 is the layout for a 30 w adapter shown in the schematic figure 11. an esip-7c package is used as indicated by the suffx in lnk6766e which allows the use of a stand-up heat sink. the mounting pin for the heat sink should be electrically isolated. it can be seen that the primary return trace wraps around the linkswitch-hp device which acts as a shield around the critical external control related components of linkswitch-hp. these components include r7, r8, r19, r20 and c5, c8, c20. of particular importance is placing the bypass capacitor c5 and compensation pin noise flter capacitor c8 as close as possible to source pin with very short trace lengths to compensation and bypass pins as shown. if an electrolytic capacitor is selected as the bypass capacitor (c5) then an additional 100 nf (c5) ceramic must also be ftted. the ground trace wrap, tight layout and single point grounding to source pin of these components avoids having noise related issues during peak loads or during line transient such as surge or esd events. another consideration for esd and line surge is the primary- side termination of the y capacitor. the y capacitor c18 should be tied to the positive terminal of the bulk capacitor c2 in order to route the potential of high currents away from the more sensitive primary return traces. because of the tight layout common to adapter applications, this design uses triple insulated wire and fying leads for output winding termination to avoid secondary arcing to core during esd events. the trace connecting the drain to transformer should be very short and the primary clamp circuitry should be grouped together and away from the more sensitive components. the bias winding return and return of bias capacitor c6 should be routed separately to the negative terminal of the input capacitor c2 away from source pin. the secondary rectifying loop that includes the secondary winding, the output diode d8, and the frst output capacitor c13 should be as tight as possible to minimize adding series inductance which can reduce high load effciency and degrade the quality of regulation. figure 12. layout for 30 w adapter using a esip-7c package (view from bottom copper layer). rev. c 03/14 linkswitch-hp www.powerint.com www.powerint.com
11 figure 14. layout for lcd monitor supply using edip-12b package. figure 13. 17 w lcd monitor supply (+18 v, +5 v). layout considerations for edip-12b package the schematic extract in figure 13 is an example of linkswitch-hp used in a dual output lcd monitor supply using edip-12b package. in this design the exposed metal tab on the topside of package is left open (no heat sink). the source pins of linkswitch-hp provide heat sinking through connection to the source copper pad of pcb. this technique is adequate for device dissipation up to 0.85 w (1/2 square inch of copper area required). the layout guidelines described for esip-7c are the same for edip-12b with an added consideration about sensitive component layout. the return referenced components c4, c8, c16, r9, r7 must be placed directly under the linkswitch-hp package as shown in figure 14. this requires that these particular components be smd type as this allows an ideal noise-immune layout. output power table assumptions ? 12 v output. ? schottky rectifcation. ? 82% effciency. ? v or = 135 v. ? k p = 0.4 for 85-265 vac input and k p = 0.6 for 195-265 vac input. ? v min = 100 v for 85-265 vac input and v min = 250 v for 195-265 vac input. ? 0.85 w device dissipation for open frame designs with pcb heat sink. quick design checklist all linkswitch-hp designs should be verifed on the bench particularly for specifed worst-case stress conditions. the following set of tests are strongly recommended: 1. maximum drain voltage C verify that vds does not exceed 675 v for lnk677x series and 600 v for lnk6x6x series. this gives a 50 v margin for design variations. 2. under all conditions, the maximum drain current should be below the specifed absolute maximum ratings. 3. thermal check C at rated maximum output power, minimum input voltage and maximum ambient temperature, verify that the maximum allowed temperature is not exceeded for any component in the design. of particular importance is checking the temperature rise of the major power conversion components such as transformer, output diodes, input bridge, primary clamp circuit and linkswitch-hp. under the stated conditions above, linkswitch-hp tab temperature should not exceed 110 c. pi-6860-120312 c9 1 nf 250 vac vr1 p6ke130a 130 v l1 10 mh br1 df06m 600 v c2 47 f 450 v d2 bav21ws- 7-f d1 dl4937 c6 22 f 25 v c8 100 pf 50 v c16 10 pf 50 v c7 100 nf 25 v c3 10 nf 630 v c12 220 f 35 v c10 470 pf 200 v d4 b340lb-13-f d3 30bq100pbf c15 470 pf 200 v c11 220 f 35 v c14 820 f 6.3 v t1 ef25 c13 820 f 6.3 v c5 4.7 f 10 v l2 ferrite bead (3.5 4.45 mm) 3 9,10 7,8 12 6 5 1 c1 100 nf 310 vac rt1 5 ? f1 2 a t o 90 - 265 vac 18 v, 0.67 a j2-6 5 v, 1a j2-1 j1-3 j1-1 rtn j2-4 linkswitch-hp d s fb bp cp pd control u1 lnk6774v r8 46.4 k? 1% 1/16 w r6 23.2 k? 1% 1/16 w r7 100 k? 1% 1/16 w r13* r5 6.98 k? 1% 1/8 w r10 10 ? 1% 1/8 w r4 20 ? 1% r3 100 ? 1% r2 100 ? 1% r1 3 k? r12 10 ? 1% 1/8 w r11 36 k? 1/8 w r9 10.5 k? 1% 1/16 w c4* *optional pi-6860-120312 rev. c 03/14 www.powerint.com linkswitch-hp
12 absolute maximum ratings (3) drain pin voltage ................................... -0.3 v to 725 v (677x) drain pin voltage .......................... -0.3 v to 650 v (666x/676x) drain pin peak current: ... ....... 1.6 x i limit(typ) (1) bypass pin voltage ............................................. -0.3 v to 9 v bypass pin current .................................................... 100 ma feedback pin voltage ....................................... -0.3 v to 9 v (2) compensation pin voltage ............................... -0.3 v to 9 v program/delay pin voltage .............................. -0.3 v to 9 v storage temperature ...................................... -65 c to 150 c operating junction temperature .................. -40 c to 150 c (4) notes: 1. peak drain current is allowed while the drain voltage is simultaneously less than 400 v. 2. -1 v for current pulses 5 ma out of the pin and a duration of 500 ns. 3. maximum ratings specifed may be applied one at a time without causing permanent damage to the product. exposure to absolute maximum rating conditions for extended periods of time may affect product reliability. 4. normally limited by internal circuitry. parameter symbol conditions source = 0 v; t j = -40 to 125 c (unless otherwise specifed) min typ max units control functions switching frequency f osc average value, t j = +25 c, 120 132 136 khz switching frequency temperature variation f osc 0 c t j +100 c, see note a 10 % frequency jitter deviation f f osc = 128 khz 5 khz frequency jitter modulation rate f m 250 hz maximum duty cycle dc max v fb < v fb(ref) v fb(ref) = 2 v t j = +25 c 62 64 66 % see note a 0 c t j +100 c +2% % maximum duty cycle temperature variation dc max minimum peak current to set current limit ratio k ps t j = +25 c di/dt (kps) = di/dt (ilimit) 22.5 25 % multi-cycle modulation switching frequency f mcm t j = +25 c 25 32 khz multi-cycle modulation max off-time t mcm(off) t j = +25 c lnk666x 0.5 ms lnk67xx 4 soft-start time t soft t j = +25 c 15 ms auto-restart shut- down default delay t sd(ar) t j = +25 c 35 ms auto-restart t ar(on) t j = +25 c, t soft + t sd(ar) 50 ms t ar(off)1 first switch off-period 150 t ar(off)2 subsequent switch off-periods 1500 thermal resistance thermal resistance: e package ( q ja ) .......................................... 105 c/w (1) ( q jc ) .............................................. 2 c/w (2) k package ( q ja ) ...........................45 c/w (3) , 38 c/w (4) ( q jc ) .............................................. 2 c/w (2) v package ( q ja ) ........................... 74 c/w (3) , 63 c/w (4) ( q jc ) .............................................. 2 c/w (2) notes: 1. free standing with no heat sink. 2. measured at the back surface of tab. 3. soldered (including exposed pad for k package) to typical application pcb with a heat sinking area of 0.36 sq. in. (232 mm 2 ), 2 oz. (610 g/m 2 ) copper clad. 4. soldered (including exposed pad for k package) to typical application pcb with a heat sinking area of 1 sq. in. (645 mm 2 ), 2 oz. (610 g/m 2 ) copper clad. rev. c 03/14 linkswitch-hp www.powerint.com www.powerint.com
13 parameter symbol conditions source = 0 v; t j = -40 to 125 c (unless otherwise specifed) min typ max units control functions (cont.) transconductance amplifer gain g m t j = +25 c 95 115 125 m a/v transconductance amplifer gain temperature variation g m 0 c t j +100 c see note a 20 % transconductance amplifer max output current i gm t j = +25 c 10.0 12.5 15.0 m a compensation pin input impedance z cp see note a 30 m w bypass (bp) input ovp/uvp/otp programming capacitor value c bp t j = +25 c see table 3 for programming 0.47 m f 4.7 47 bypass pin voltage v bp 5.46 5.75 6.04 v bypass pin voltage hysteresis v bph 0.85 0.95 1.1 v bypass pin charge current i ch1 v bp = 0 v t j = +25 c v ds 50 v lnk6xx3 -6.8 -4.8 -2.0 ma lnk6xx4-5 -9.2 -6.6 -2.8 lnk6xx6-7 -12.0 -8.3 -4.3 i ch2 v bp = 5 v t j = +25 c v ds 50 v lnk6xx3 -4.7 -2.7 -1.5 ma lnk6xx4-5 -7.0 -4.0 -2.2 lnk6xx6-7 -8.8 -5.2 -2.9 bypass pin shutdown threshold current i bpsd t j = +25 c 5.7 8.2 10.7 ma bypass pin shutdown delay t j = +25 c 8 switching cycles bypass pin source current i bpsc v bp = 6 v t j = +25 c -0.5 ma bypass pin charge current temperature variation i bpsc see note a 0.5 %/ c bypass pin shunt voltage v bp(shunt) i bp = 2 ma 6.1 6.4 6.7 v bypass pin supply current i bps1 t j = +25 c, see note b 525 m a i bps2 mosfet switching at f osc lnkxxx3 0.9 1.2 ma lnkxxx4 1.0 1.3 lnkxxx5 1.1 1.4 lnkxxx6 1.3 1.6 lnkxxx7 1.4 1.7 rev. c 03/14 www.powerint.com linkswitch-hp
14 parameter symbol conditions source = 0 v; t j = -40 to 125 c (unless otherwise specifed) min typ max units voltage sense (fb) input feedback pin reference voltage v fbth t j = +25 c 1.974 2.000 2.026 v feedback pin reference voltage temperature variation v fb(th) 0 c t j +100 c see note a -0.01 %/ c line undervoltage turn-on threshold current i fb(uv,ref) t on = 220 ns, t j = +25 c -250 m a feedback pin bus voltage reference current temperature variation i fb(ref) t on = 220 ns, 0 c t j +100 c see note a 10 % line undervoltage turn-off threshold current i fb(uvoff) t on = 220 ns, t j = +25 c -115 -100 -85 m a line undervoltage turn-off delay t j = 25 c 8 switching cycles line overvoltage turn-off threshold current i fb(ov) t on = 220 ns, t j = +25 c -1200 -1150 -1100 m a line overvoltage turn-off delay t j = +25 c 2 switching cycles output overvoltage detection threshold voltage v fb(ovp) t j = +25 c 2.375 2.5 2.625 v output overvoltage detection delay t j = +25 c 16 switching cycles feedback pin auto-restart threshold voltage v fb(ar) t j = +25 c 1.794 1.85 1.906 v current limit reduction onset threshold current i fb(lim) t on = 220 ns, t j = +25 c -210 m a current limit reduction slope i lim(line) 0 c t j +100 c -463 m a < i fb i fb(lim) -0.032 %/ m a i fb < -463 m a -0.008 feedback pin sampling delay time t samp1 0 c t j +100 c i pk = i set 2.5 2.65 m s t samp2 i pk = 0.25 i set 1.2 1.3 missing feedback voltage protection sense delay time t mfvp t j = +25 c 0.8 m s missing feedback voltage protection delay 4 switching cycles rev. c 03/14 linkswitch-hp www.powerint.com www.powerint.com
15 parameter symbol conditions source = 0 v; t j = -40 to 125 c (unless otherwise specifed) min typ max units multi-function (pd) input program/delay pin voltage v pd t j = +25 c 1.20 1.25 1.30 v program/delay pin time lower voltage threshold v pd(dl) t j = +25 c 0.50 0.535 0.57 v program/delay pin time upper voltage threshold v pd(du) t j = +25 c 1.20 1.25 1.30 v fast ac reset threshold v pdthacr 3.06 3.4 3.74 v remote on/off threshold v pdthrm t j = +25 c threshold 1.25 1.35 1.45 v hysteresis 0.8 remote on/off delay t j = +25 c 8 switching cycles circuit protection self protection current limit i limit lnk6xx3 di/dt = 180 ma/ m s t j = +25 c 0.716 0.77 0.824 a lnk6xx4 di/dt = 245 ma/ m s t j = +25 c 0.967 1.04 1.113 lnk6xx5 di/dt = 305 ma/ m s t j = +25 c 1.209 1.30 1.391 lnk6xx6 di/dt = 460 ma/ m s t j = +25 c 1.814 1.95 2.087 lnk6xx7 di/dt = 610 ma/ m s t j = +25 c 2.418 2.60 2.782 programmed current limit variation i limit see table 3 for programming 0 c t j +100 c, see note a 7 % operational peak current variation i pk(op) i pk(op) = 25 -100% i limit , 0 c t j +100 c, see note a 7 % thermal shutdown temperature t sd 135 142 150 c thermal shutdown hysteresis t sdh c bp = 0.47 m f or c bp = 4.7 m f 75 c leading edge blanking time t leb t j = +25 c see note a 175 220 ns current limit delay time t ild t j = +25 c 100 ns minimum switch on-time t on(min) t leb(max) + t ild(max) t j = +25 c 325 400 500 ns rev. c 03/14 www.powerint.com linkswitch-hp
16 parameter symbol conditions source = 0 v; t j = -40 to 125 c (unless otherwise specifed) min typ max units output on-state resistance r ds(on) lnk6xx3 i d = 100 ma t j = +25 c 6.9 7.97 w t j = +100 c 10.5 12.08 lnk6xx4 i d = 150 ma t j = +25 c 4.6 5.30 t j = +100 c 7.0 8.09 lnk6xx5 i d = 200 ma t j = +25 c 3.5 4.03 t j = +100 c 5.4 6.21 lnk6xx6 i d = 300 ma t j = +25 c 2.3 2.65 t j = +100 c 3.6 4.14 lnk6xx7 i d = 400 ma t j = +25 c 1.8 2.07 t j = +100 c 2.7 3.11 off-state drain leakage current i dss v pd = floating v ds = 560 v, t j = 125 c 470 m a v ds = 325 v, t j = 100 c 10 breakdown voltage bv dss lnk677x, v pd = floating, t j = +25 c 725 v lnk666x/lnk676x, v pd = floating, t j = +25 c 650 drain supply voltage 50 v rise time t r measured in a typical fyback converter application 100 ns fall time t f 50 notes: a. parameter not tested over specifed temperature range. guaranteed by design and characterization. b. average device switching frequency below 1 khz. rev. c 03/14 linkswitch-hp www.powerint.com www.powerint.com
17 figure 15. duty cycle measurement. rev. c 03/14 www.powerint.com linkswitch-hp
18 typical performance characteristics figure 17. standard current limit vs. temperature. figure 18. output characteristic. figure 19. c oss vs. drain voltage. figure 20. drain capacitance power. drain voltage (v) drain capacitance (pf) pi-6851-071912 0 100 200 300 400 500 600 1 10 100 1000 lnk6xx3 1 lnk6xx4 1.5 lnk6xx5 2 lnk6xx6 3 lnk6xx7 4 scaling factors: drain voltage (v) power (mw) pi-6852-071912 0 100 200 300 400 500 600 0 40 80 120 160 lnk6xx3 1 lnk6xx4 1.5 lnk6xx5 2 lnk6xx6 3 lnk6xx7 4 scaling factors: drain voltage (v) drain current (ma) 1200 1000 800 400 200 600 0 0 2 4 6 8 10 t case =25 c t case =100 c pi-6850-071912 lnk6xx3 1 lnk6xx4 1.5 lnk6xx5 2 lnk6xx6 3 lnk6xx7 4 scaling factors: temperature (c) standard current limit (normalized to 25 c) 1.05 1.00 95 90 85 80 -40 0 -20 20 40 60 80 100 120 pi-6787-053112 figure 16. breakdown vs. temperature. 1.1 1.0 0.9 -50 -25 02 55 07 5 100 125 150 junction temperature (q c) breakdown voltage (normalized to 25 q c) pi-2213-012301 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 150 junction temperature ( c) pi-6853-071812 output frequency (normalized to 25 c) figure 21. frequency vs. temperature. rev. c 03/14 linkswitch-hp www.powerint.com www.powerint.com
19 typical performance characteristics figure 27. maximum allowable drain current vs. drain voltage (lnk6763-6767/lnk6663-6667). figure 26. maximum allowable drain current vs. drain voltage (lnk6773-6777). 0 0 100 200 300 400 600 500 700 800 drain voltage (v) drain current (normalized to absolute maximum rating) pi-6010-060410 0.6 0.8 0.4 0.2 1 1.2 0 0 100 200 300 500 400 600 700 drain voltage (v) drain current (normalized to absolute maximum rating) pi-6731-040212 0.6 0.8 0.4 0.2 1 1.2 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 150 junction temperature ( c) pi-4761-061407 overvoltage threshold (normalized to 25 c) 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 150 junction temperature ( c) pi-6854-071812 undervoltage threshold (normalized to 25 c) figure 22. overvoltage threshold vs. temperature. figure 24. overvoltage threshold vs. temperature. figure 23. undervoltage threshold vs. temperature. figure 25. undervoltage threshold vs. temperature. 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 150 junction temperature ( c) pi-6855-071812 undervoltage turn-on threshold (normalized to 25 c) 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 150 junction temperature ( c) pi-6856-071812 undervoltage turn-off threshold (normalized to 25 c) rev. c 03/14 www.powerint.com linkswitch-hp
20 pi-4917-061510 mounting hole pattern (not to scale) pin 7 pin 1 0.100 (2.54) 0.100 (2.54) 0.059 (1.50) 0.059 (1.50) 0.050 (1.27) 0.050 (1.27) 0.100 (2.54) 0.155 (3.93) 0.020 (0.50) notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. dimensions noted are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs, and interlead flash, but including any mismatch between the top and bottom of the plastic body. maximum mold protrusion is 0.007 [0.18] per side. 3. dimensions noted are inclusive of plating thickness. 4. does not include inter-lead flash or protrusions. 5. controlling dimensions in inches (mm). 0.403 (10.24) 0.397 (10.08) 0.325 (8.25) 0.320 (8.13) 0.050 (1.27) front view 2 2 b a 0.070 (1.78) ref. pin #1 i.d. 3 c 0.016 (0.41) ref. 0.290 (7.37) ref. 0.047 (1.19) 0.100 (2.54) 0.519 (13.18) ref. 0.198 (5.04) ref. 0.264 (6.70) ref. 0.118 (3.00) 6 6 3 0.140 (3.56) 0.120 (3.05) 0.021 (0.53) 0.019 (0.48) 0.378 (9.60) ref. 0.019 (0.48) ref. 0.060 (1.52) ref. 0.048 (1.22) 0.046 (1.17) 0.081 (2.06) 0.077 (1.96) 0.207 (5.26) 0.187 (4.75) 0.033 (0.84) 0.028 (0.71) 0.016 (0.41) 0.011 (0.28) esip-7c (e package) 10 ref. all around 0.020 m 0.51 m c 0.010 m 0.25 m c a b side view end view back view 4 0.023 (0.58) 0.027 (0.70) detail a detail a rev. c 03/14 linkswitch-hp www.powerint.com www.powerint.com
21 side view end view 11 2 7 7 pi-5748a-100311 notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. dimensions noted are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs, and interlead flash, but including any mismatch between the top and bottom of the plastic body. maximum mold protrusion is 0.007 [0.18] per side. 3. dimensions noted are inclusive of plating thickness. 4. does not include interlead flash or protrusions. 5. controlling dimensions in inches [mm]. 6. datums a and b to be determined at datum h. 7. exposed pad is nominally located at the centerline of datums a and b. ?max? dimensions noted include both size and positional tolerances. esop-12b (k package) b c c h top view bottom view pin #1 i.d. (laser marked) 0.023 [0.58] 0.018 [0.46] 0.006 [0.15] 0.000 [0.00] 0.098 [2.49] 0.086 [2.18] 0.092 [2.34] 0.086 [2.18] 0.032 [0.80] 0.029 [0.72] seating plane detail a seating plane to package bottom standoff 0.034 [0.85] 0.026 [0.65] 0.049 [1.23] 0.046 [1.16] 3 4 0.460 [11.68] 0.400 [10.16] 0.070 [1.78] 0.306 [7.77] ref. 2 0.350 [8.89] 0.010 [0.25] ref. gauge plane seating plane 0.055 [1.40] ref. 0.010 [0.25] 0.059 [1.50] ref, typ 0.225 [5.72] max. 0.019 [0.48] ref. 0.022 [0.56] ref. 0.020 [0.51] ref. 0.028 [0.71] ref. 0.325 [8.26] max. 0.356 [9.04] ref. 0.059 [1.50] ref, typ 0.120 [3.05] ref 0.010 (0.25) m c a b 11 0.016 [0.41] 0.011 [0.28] 3 detail a (scale = 9x) 0.008 [0.20] c 2x, 5/6 lead tips 0.004 [0.10] c 0.004 [0.10] c a 2x 0.004 [0.10] c b 0 - 8 1 2 3 4 6 6 1 7 12 2x 0.217 [5.51] 0.321 [8.15] 0.429 [10.90] 0.028 [0.71] 0.067 [1.70] land pattern dimensions 11 12 10 9 8 7 2 1 3 4 6 rev. c 03/14 www.powerint.com linkswitch-hp
22 side view c a end view 11 11 detail a 0.059 [1.50] ref, typ. 2 8 notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. dimensions noted are determined at the outer- most extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs, and interlead flash, but including any mismatch between the top and bottom of the plastic body. maximum mold protrusion is 0.007 [0.18] per side. 3. dimensions noted are inclusive of plating thickness. 4. does not include inter-lead flash or protrusions. 5. controlling dimensions in inches [mm]. 6. datums a and b to be determined at datum h. 7. measured with the leads constrained to be perpendicular to datum c. 8. measured with the leads unconstrained. 9. lead numbering per jedec spp-012. 10. exposed pad is nominally located at the center- line of datums a and b. ?max? dimensions noted include both size and positional tolerances. edip-12b (v package) b h top view 0.325 [8.26] max. pin #1 i.d. (laser marked) 0.350 [8.89] 0.070 [1.78] 1 2 3 4 6 12 11 10 9 8 7 7 12 6 0.059 [1.50] ref, typ. 1 0.225 [5.72] max. 0.192 [4.87] ref. 0.436 [11.08] 0.406 [10.32] 0.023 [0.58] 0.018 [0.46] 0.092 [2.34] 0.086 [2.18] 0.049 [1.23] 0.046 [1.16] 0.022 [0.56] ref. 0.031 [0.80] 0.028 [0.72] 0.016 [0.41] 0.011 [0.28] 0.400 [10.16] 7 2 3 4 10 10 0.400 [10.16] 0.010 [0.25] ref. seating plane 0.412 [10.46] ref. 0.120 [3.05] ref. 0.306 [7.77] ref. 0.104 [2.65] ref. 0.356 [9.04] ref. 0.019 [0.48] ref. 0.028 [0.71] ref. 0.020 [0.51] ref. bottom view 0.010 [0.25] m c a b 2x 0.004 [0.10] c b detail a (scale = 9x) 0.004 [0.10] c a 5 4 pi-5556a-100311 0.07 [1.78] 0.03 [0.76] 0.400 [10.16] mounting hole pattern dimensions drill hole 0.03 [0.76] round pad 0.05 [1.27] solder mask 0.056 [1.42] rev. c 03/14 linkswitch-hp www.powerint.com www.powerint.com
23 part ordering information ? linkswitch product family ? hp series number ? package identifer e esip-7c k esop-12b v edip-12b ? tape & reel and other options blank standard confgurations tl tape & reel lnk 6xx7 e tl rev. c 03/14 www.powerint.com linkswitch-hp
revision notes date a initial release. 08/12 a updated table 2. 08/23/12 a updated page 5. 10/24/12 b formatting changes. k ps min value updated. 12/04/12 b fixed table references. 02/26/13 c released k package parts. updated v fb(th) typ value on page 14. 03/14 for the latest updates, visit our website: www.powerint.com power integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. power integrations does not assume any liability arising from the use of any device or circuit described herein. power integrations makes no warranty herein and specifically disclaims all warranties including, without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement of third party rights. patent information the products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or more u.s. and foreign patents, or potentially by pending u.s. and foreign patent applications assigned to power integrations. a complete list of power integrations patents may be found at www.powerint.com. power integrations grants its customers a license under certain patent rights as set forth at http://www.powerint.com/ip.htm. life support policy power integrations products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of power integrations. as used herein: 1. a life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in signifcant injury or death to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. the pi logo, topswitch, tinyswitch, linkswitch, lytswitch, dpa-switch, peakswitch, capzero, senzero, linkzero, hiperpfs, hipertfs, hiperlcs, qspeed, ecosmart, clampless, e-shield, filterfuse, stakfet, pi expert and pi facts are trademarks of power integrations, inc. other trademarks are property of their respective companies. ?2014, power integrations, inc. power integrations worldwide sales support locations world headquarters 5245 hellyer avenue san jose, ca 95138, usa. main: +1-408-414-9200 customer service: phone: +1-408-414-9665 fax: +1-408-414-9765 e-mail: usasales@powerint.com china (shanghai) rm 2410, charity plaza, no. 88 north caoxi road shanghai, prc 200030 phone: +86-21-6354-6323 fax: +86-21-6354-6325 e-mail: chinasales@powerint.com china (shenzhen) 3rd floor, block a, zhongtou international business center, no. 1061, xiang mei rd, futian district, shenzhen, china, 518040 phone: +86-755-8379-3243 fax: +86-755-8379-5828 e-mail: chinasales@powerint.com germany lindwurmstrasse 114 80337 munich germany phone: +49-895-527-39110 fax: +49-895-527-39200 e-mail: eurosales@powerint.com india #1, 14th main road vasanthanagar bangalore-560052 india phone: +91-80-4113-8020 fax: +91-80-4113-8023 e-mail: indiasales@powerint.com italy via milanese 20, 3rd. fl. 20099 sesto san giovanni (mi) italy phone: +39-024-550-8701 fax: +39-028-928-6009 e-mail: eurosales@powerint.com japan kosei dai-3 bldg. 2-12-11, shin-yokohama, kohoku-ku yokohama-shi kanagwan 222-0033 japan phone: +81-45-471-1021 fax: +81-45-471-3717 e-mail: japansales@powerint.com korea rm 602, 6fl korea city air terminal b/d, 159-6 samsung-dong, kangnam-gu, seoul, 135-728, korea phone: +82-2-2016-6610 fax: +82-2-2016-6630 e-mail: koreasales@powerint.com singapore 51 newton road #19-01/05 goldhill plaza singapore, 308900 phone: +65-6358-2160 fax: +65-6358-2015 e-mail: singaporesales@powerint.com taiwan 5f, no. 318, nei hu rd., sec. 1 nei hu dist. taipei 11493, taiwan r.o.c. phone: +886-2-2659-4570 fax: +886-2-2659-4550 e-mail: taiwansales@powerint.com europe hq 1st floor, st. jamess house east street, farnham surrey gu9 7tj united kingdom phone: +44 (0) 1252-730-141 fax: +44 (0) 1252-727-689 e-mail: eurosales@powerint.com applications hotline world wide +1-408-414-9660 applications fax world wide +1-408-414-9760

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